According to the present situation that bit rate of information to be processed by a field effect transistor (FET, hereinafter) is remarkably increasing and requirement for miniaturizing the FET becomes noticeable, development of the FET having a short channel is regarded as important. In conformity with the aforementioned tendency, it becomes necessary to form the shallow source and drain junctions of the FET. As a process for forming the shallow source and drain regions of the FET, a method for selectively growing a Si epitaxial layer on a substrate, where the source and drain regions are to be formed, has been proposed. Although it is important to establish methods for forming the shallow source and drain junctions for both the n- and p-channel FETs, formation of the same for the p-channel FET is especially difficult.
If B or BF.sub.3 ions are implanted on the Si epitaxial layer and thermal treatment is applied thereto, the source and drain regions of the p-channel FET can be formed, but the shallow junctions cannot be obtained for the reason mentioned later.
If B is substituted for n-type impurity, such as P or As, the source and drain regions of an n-channel FET can be formed. The depth of the source and drain junctions of the n-channel FET thus obtained are shallower than those of the p-channel FET obtained by B ion implantation, because diffusion constant of the n-type impurity, such as P or As, in the implanted Si-substrate is smaller than that of B.
However, it is known that if the Si epitaxial layer for the p-channel FET is doped with B and this impurity is thermally diffused into the Si-substrate, a shallow source and drain junctions of the p-channel FET can be obtained.
In order to fabricate a complementary metal oxide semiconductor (COMS, hereinafter) device with the shallow source and drain junctions, it is extremely desirable to combine the two aforementioned methods for forming the source and drain junctions respectively suited for the n- and p-channel FETs.